Charge pump circuits are normally employed in phase locked loop circuits and selectively provide current to a loop filter or receive current from the filter. Such current generation and reception causes a voltage controlled oscillator to produce an output signal having a desired frequency.
Specifically, charge pump circuits receive an error signal corresponding to a phase difference between a reference signal and the output signal. The error signal specifies frequency modifications necessary to make the frequency of the output signal substantially identical to the reference signal frequency.
If the output frequency is to be increased, the charge pump circuit selectively sources or increases the amount of current generated to the loop filter. Alternatively, if the frequency is to be decreased, the charge pump sinks or receives a certain amount of current from the loop filter. In many instances, current is both sourced and sunk in order to make desired frequency modifications. Such current sourcing and sinking respectively increases and decreases the potential or voltage of the loop filter which is applied to the voltage controlled oscillator. These voltage modifications cause the oscillator to vary the frequency of the output signal in the desired manner.
While many conventional charge pump circuits adequately and desirably modify the output signal frequency, they also suffer from many drawbacks. For example, it is not uncommon for a given charge pump to have non-identical current generating and sinking circuits and to therefore generate and absorb non-identical amounts of current. Such disparity causes these charge pumps to incorrectly modify the output signal frequency.
Moreover, these unique current generating and sinking circuits usually have unequal activation time intervals with respect to the time at which a correction signal was received. Such activation disparity increases the time necessary to produce an output signal having a desired frequency and increases phase noise and spurious frequency generation. Many conventional charge pump circuits also utilize elements which consume relatively large amounts of power and have current amplitudes which vary in proportion to variations in one or more voltage supplies. This further adds to the overall unreliability of these devices.
To understand prior charge pump operation reference is now made to FIG. 1, where there is shown a phase correction signal generator 10 made in accordance with the teachings of the prior art. As shown, generator 10 includes a typical loop filter 25 which is connected to a voltage controlled oscillator 41. Generator 10 also includes a phase comparator 12 which receives a reference signal 14 and the output signal 16 generated by the voltage controlled oscillator 41. Comparator 12 compares the phase of signal 14 with the phase of signal 16 and, in response thereto, outputs frequency correction signals 20 and 22.
Signals 20 and 22 are input to charge pump circuit 24 and are respectively effective, when they are in a first logical state (i.e. logically high), to cause pump 24 to absorb or sink current from filter 25 and to cause pump 24 to output or source current to filter 25. When current is concomitantly sourced and sunk, signal 18 is generated by charge pump 24 and causes signals 20 and 22 to be of a second and opposite logical state (i.e. logically low), thereby preventing further current sinking or sourcing.
To illustrate some of the previously-described difficulties associated with prior charge pump circuits, reference is now made to FIG. 2 where there is shown a charge pump circuit 24' made in accordance with the teachings of the prior art. As shown, circuit 24' includes a cascaded arrangement of inverters 26, 28, and 30 which cooperatively receive and invert signal 22 and apply the inverted signal to the gate of a typical PMOS field effect transistor 33.
Circuit 24' further includes a second cascaded arrangement of inverters 31 and 32 which receive signal 20 and apply signal 20 to the gate of NMOS transistor 34. The respective source terminals of transistors 32 and 34 are coupled to a voltage source 36 and to electrical ground 38. Transistors 32 and 34 are mutually coupled at their respective drain terminals. These coupled drain terminals provide the output signal 40' which is coupled to the loop filter.
In operation, as will be known to those of ordinary skill in the art, signal 22, when logically high, activates transistor 33. Such transistor activation causes current to flow from the voltage source 36 through tile drain of transistor 33 and onto bus 40'. Signal 20, when logically high, activates transistor 34. Such transistor activation provides a current path from bus 40' to electrical ground 38. Concomitant deactivation of transistors 33 and 34 (i.e. when signals 20 and 22 are each logically low) places bus 40' in a tri or high impedance state and prevents current from either sourced or sunk.
As will be appreciated, inverters 26, 28, and 32 cooperate with transistor 33 to selectively generate current to bus 40' while inverters 30 and 32 cooperate with transistor 34 to provide a "current sink" circuit. Since these circuits are dissimilar (i.e. each having a different number of circuit elements 26, 28, 30 and 31, 32), they activate respective transistors 33 and 34 at different time intervals after receipt of respective signals 22, 20. These different activation time intervals are caused by the cumulative delay differences between the respective first phase comparator output signal reception element (i.e. 26 or 30) and the respective target transistor (i.e. 33 or 34). These delay disparities result in many of the previously-discussed difficulties.
Moreover, since transistors 33 and 34 are normally operated in a low impedance output state it is difficult, due to transistor fabrication constraints, to match such dissimilar N-type and P-type transistors. Such matching difficulties in combination with variations in the current output from the voltage source causes unequal current source and sink amplitudes. It should be apparent to those of ordinary skill in the art that such amplitude differences will degrade charge pump performance.
Referring now to FIG. 3, there is shown a second prior art charge pump circuit 24" which differs from circuit 24' by the use of bipolar transistors 35 and 37 and respective biasing resistors 39, 41, 42, and 43 in place of transistors 33 and 34. Specifically, resistors 42 and 43 are respectively coupled to the base and emitter of transistors 35 and 37. Resistors 41 and 39 are respectively coupled to inverters 30' and 32' and to resistors 42 and 43.
The operation of circuit 24" is substantially similar to that of circuit 24' in that logically high signals 22 and 20 respectively cause current to flow from the collector of transistors 35 and 37, thereby selectively sourcing and sinking current. When signals 22 and 20 are logically low, resistor pairs 41, 42 and 39, 43 respectively provide a path which applies the potential of source 36' to the base of transistor 35 and discharges current from the base of transistor 37 to ground, thereby preventing substantially any current from being sourced or sunk.
While circuit 24" adequately and selectively sources and sinks current it suffers from the same drawbacks as previously described with respect to circuit 24'. Moreover, it should be appreciated that circuits 24' and 24" have been described without reference to the manner in which signal 18 (shown and previously described with reference to FIG. 1) is generated. Such description is not necessary to adequately illustrate the various deficiencies associated with these prior charge pump circuits.
Therefore, there is a need to provide a charge pump circuit having substantially identical source and sink current amplitudes, substantially identical source and sink activation time intervals, relatively low static power utilization, and having currents that are relatively insensitive to variations in voltage supply output current.